1. Field of the Invention
The present invention relates in general to the field of data processing circuitry and, more specifically, to systems and methods for providing an improved first-in-first-out (FIFO) and last-in last-out (LIFO) data buffer.
2. Description of the Related Art
A FIFO buffer is a common digital block used when data needs to be transferred between two blocks of a digital system. A typical FIFO has an array of memory in which data is stored. The memory is accessed using read and write pointers which define the location of memory that needs to be read-out or written-in. The read and write pointers need to be decoded to generate the wordlines to access the memory. A generalized decoder typically is used to decode the wordlines, thereby allowing decoding of the pointers in any order. The read and write pointers in a FIFO buffer follow a pattern; however, prior-art decoder circuits do not take advantage of this pattern to optimize decoding.
A LIFO buffer uses a single pointer for both read and write. On reset, the pointer is initialized to the first element and the LIFO is EMPTY. In a write operation, the pointer is first incremented and write occurs on the address indicated by the new incremented value of the pointer. If the pointer reaches the last element, the LIFO is FULL. In a read operation, the read occurs on the address indicated by current value of pointer and the pointer is then decremented. If the pointer reaches the first element, the LIFO is EMPTY again. From the decoder perspective a single decoder common to both read/write is used and the address which it receives for decoding depends on the read or write.
Most prior-art decoders use a generalized N to 2N decoder, which can decode the pointers in any order. These decoders consist of a series of AND/NAND gates, with the number of gates being directly related to the number of bits to be decoded. The total delay of the wordline generation depends on the size of decoder, since the higher the number of bits to be decoded, higher the delay will be because of the larger number of AND/NAND gates need in the path used to the generate the wordline.
In view of the foregoing, it is apparent that there is a need for improved systems and methods for an optimized decoder that efficiently decodes addresses in a buffer to reduce the delay in the paths used to generate wordlines.
Where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.